Changeset 161
- Timestamp:
- 07.11.2008 16:45:25 (2 months ago)
- Files:
-
- trunk/boards/xilinx-ml401/ddram.v (modified) (3 diffs)
- trunk/boards/xilinx-ml401/system.v (modified) (23 diffs)
- trunk/cores/brg64 (added)
- trunk/cores/brg64/brg64.v (added)
- trunk/cores/warp/doc/warp_algo.tex (added)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
trunk/boards/xilinx-ml401/ddram.v
r160 r161 50 50 output sdram_clk_p, 51 51 output sdram_clk_n, 52 input sdram_clk_fb, 52 53 output sdram_cke, 53 54 output sdram_cs_n, … … 100 101 ); 101 102 103 DCM_BASE #( 104 .CLKDV_DIVIDE(1.5), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 105 106 .CLKFX_DIVIDE(3), // 1 to 32 107 .CLKFX_MULTIPLY(2), // 2 to 32 108 109 .CLKIN_DIVIDE_BY_2("FALSE"), 110 .CLKIN_PERIOD(`CLOCK_PERIOD), 111 .CLKOUT_PHASE_SHIFT("NONE"), 112 .CLK_FEEDBACK("1X"), 113 .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), 114 .DFS_FREQUENCY_MODE("LOW"), 115 .DLL_FREQUENCY_MODE("LOW"), 116 .DUTY_CYCLE_CORRECTION("TRUE"), 117 .FACTORY_JF(16'hC080), 118 .PHASE_SHIFT(0), 119 .STARTUP_WAIT("TRUE") 120 ) clkgen_sdram ( 121 .CLK0(sdram_clk_p), 122 .CLK90(), 123 .CLK180(sdram_clk_n), 124 .CLK270(), 125 126 .CLK2X(), 127 .CLK2X180(), 128 129 .CLKDV(), 130 .CLKFX(), 131 .CLKFX180(), 132 .LOCKED(), 133 .CLKFB(sdram_clk_fb), 134 .CLKIN(sys_clk), 135 .RST(1'b0) 136 ); 137 138 102 139 hpdmc #( 103 140 .sdram_depth(SDRAM_DEPTH), … … 151 188 assign wb_dat_o = 64'hcafebabedeafbeef; 152 189 153 assign sdram_clk = 1'b0; 190 assign sdram_clk_p = 1'b0; 191 assign sdram_clk_n = 1'b0; 154 192 assign sdram_cke = 1'b0; 155 193 assign sdram_cs_n = 1'b1; trunk/boards/xilinx-ml401/system.v
r160 r161 83 83 // Clock and Reset Generation 84 84 //------------------------------------------------------------------ 85 wire clk;86 87 assign clk = clkin;85 wire sys_clk; 86 87 assign sys_clk = clkin; 88 88 89 89 reg rst0; 90 90 reg rst1; 91 always @(posedge clk) rst0 <= resetin;92 always @(posedge clk) rst1 <= rst0;91 always @(posedge sys_clk) rst0 <= resetin; 92 always @(posedge sys_clk) rst1 <= rst0; 93 93 reg [15:0] rst_debounce; 94 reg rst;95 always @(posedge clk) begin94 reg sys_rst; 95 always @(posedge sys_clk) begin 96 96 if(~rst1) /* reset active low */ 97 97 rst_debounce <= 16'hFFFF; 98 98 else if(rst_debounce != 16'h0000) 99 99 rst_debounce <= rst_debounce - 16'h0001; 100 rst <= rst_debounce != 16'h0000;100 sys_rst <= rst_debounce != 16'h0000; 101 101 end 102 102 … … 106 106 wire [31:0] cpuibus_adr, 107 107 cpudbus_adr; 108 wire [2:0] cpuibus_cti, 109 cpudbus_cti; 108 110 wire [31:0] cpuibus_dat_r, 109 111 cpuibus_dat_w, … … 124 126 // Wishbone slave wires (Low-speed) 125 127 //------------------------------------------------------------------ 126 wire [31:0] uart_adr, 128 wire [31:0] brg_adr, 129 bram_adr, 130 uart_adr, 131 gpio_adr, 132 aceusb_adr, 133 hpdmc_adr, 134 intc_adr, 135 vga_adr, 136 ac97_adr, 127 137 shader_adr, 128 gpio_adr,129 bram_adr,130 hpdmc_adr,131 vga_adr,132 aceusb_adr,133 138 warp_adr; 134 139 135 wire [31:0] uart_dat_r, 140 wire [2:0] brg_cti, 141 bram_cti, 142 uart_cti, 143 gpio_cti, 144 aceusb_cti, 145 hpdmc_cti, 146 intc_cti, 147 vga_cti, 148 ac97_cti, 149 shader_cti, 150 warp_cti; 151 152 wire [31:0] brg_dat_r, 153 brg_dat_w, 154 bram_dat_r, 155 bram_dat_w, 156 uart_dat_r, 136 157 uart_dat_w, 158 gpio_dat_r, 159 gpio_dat_w, 160 aceusb_dat_r, 161 aceusb_dat_w, 162 hpdmc_dat_r, 163 hpdmc_dat_w, 164 intc_dat_r, 165 intc_dat_w, 166 vga_dat_r, 167 vga_dat_w, 168 ac97_dat_r, 169 ac97_dat_w, 137 170 shader_dat_r, 138 171 shader_dat_w, 139 gpio_dat_r,140 gpio_dat_w,141 bram_dat_r,142 bram_dat_w,143 hpdmc_dat_w,144 hpdmc_dat_r,145 vga_dat_w,146 vga_dat_r,147 aceusb_dat_w,148 aceusb_dat_r,149 172 warp_dat_w, 150 173 warp_dat_r; 151 174 152 wire [3:0] uart_sel, 175 wire [3:0] brg_sel, 176 bram_sel, 177 uart_sel, 153 178 gpio_sel, 154 bram_sel, 179 aceusb_sel, 180 hpdmc_sel, 181 intc_sel, 155 182 vga_sel, 156 aceusb_sel, 157 hpdmc_sel; 158 159 wire uart_we, 183 ac97_sel, 184 shader_sel, 185 warp_sel; 186 187 wire brg_we, 188 bram_we, 189 uart_we, 190 gpio_we, 191 aceusb_we, 192 hpdmc_we, 193 intc_we, 194 vga_we, 195 ac97_we, 160 196 shader_we, 161 gpio_we,162 bram_we,163 hpdmc_we,164 vga_we,165 aceusb_we,166 197 warp_we; 167 198 168 wire uart_cyc, 199 wire brg_cyc, 200 bram_cyc, 201 uart_cyc, 202 gpio_cyc, 203 aceusb_cyc, 204 hpdmc_cyc, 205 intc_cyc, 206 vga_cyc, 207 ac97_cyc, 169 208 shader_cyc, 170 gpio_cyc,171 bram_cyc,172 hpdmc_cyc,173 vga_cyc,174 aceusb_cyc,175 209 warp_cyc; 176 210 177 wire uart_stb, 211 wire brg_stb, 212 bram_stb, 213 uart_stb, 214 gpio_stb, 215 aceusb_stb, 216 hpdmc_stb, 217 intc_stb, 218 vga_stb, 219 ac97_stb, 178 220 shader_stb, 179 gpio_stb,180 bram_stb,181 hpdmc_stb,182 vga_stb,183 aceusb_stb,184 221 warp_stb; 185 222 186 wire uart_ack, 223 wire brg_ack, 224 bram_ack, 225 uart_ack, 226 gpio_ack, 227 aceusb_ack, 228 hpdmc_ack, 229 intc_ack, 230 vga_ack, 231 ac97_ack, 187 232 shader_ack, 188 gpio_ack,189 bram_ack,190 hpdmc_ack,191 vga_ack,192 aceusb_ack,193 233 warp_ack; 194 234 … … 211 251 .sa_addr ( 8'h09 ) // warp 212 252 ) conmax0 ( 213 .clk_i( clk),214 .rst_i( rst),253 .clk_i(sys_clk), 254 .rst_i(sys_rst), 215 255 // Master0 216 256 .m0_dat_i(cpuibus_dat_w), … … 290 330 .s0_dat_o(brg_dat_w), 291 331 .s0_adr_o(brg_adr), 332 .s0_cti_o(brg_cti), 292 333 .s0_sel_o(brg_sel), 293 334 .s0_we_o(brg_we), … … 299 340 .s1_dat_o(bram_dat_w), 300 341 .s1_adr_o(bram_adr), 342 .s1_cti_o(bram_cti), 301 343 .s1_sel_o(bram_sel), 302 344 .s1_we_o(bram_we), … … 308 350 .s2_dat_o(uart_dat_w), 309 351 .s2_adr_o(uart_adr), 352 .s2_cti_o(uart_cti), 310 353 .s2_sel_o(uart_sel), 311 354 .s2_we_o(uart_we), … … 317 360 .s3_dat_o(gpio_dat_w), 318 361 .s3_adr_o(gpio_adr), 362 .s3_cti_o(gpio_cti), 319 363 .s3_sel_o(gpio_sel), 320 364 .s3_we_o(gpio_we), … … 326 370 .s4_dat_o(aceusb_dat_w), 327 371 .s4_adr_o(aceusb_adr), 372 .s4_cti_o(aceusb_cti), 328 373 .s4_sel_o(aceusb_sel), 329 374 .s4_we_o(aceusb_we), … … 335 380 .s5_dat_o(hpdmc_dat_w), 336 381 .s5_adr_o(hpdmc_adr), 382 .s5_cti_o(hpdmc_cti), 337 383 .s5_sel_o(hpdmc_sel), 338 384 .s5_we_o(hpdmc_we), … … 344 390 .s6_dat_o(intc_dat_w), 345 391 .s6_adr_o(intc_adr), 392 .s6_cti_o(intc_cti), 346 393 .s6_sel_o(intc_sel), 347 394 .s6_we_o(intc_we), … … 353 400 .s7_dat_o(vga_dat_w), 354 401 .s7_adr_o(vga_adr), 402 .s7_cti_o(vga_cti), 355 403 .s7_sel_o(vga_sel), 356 404 .s7_we_o(vga_we), … … 362 410 .s8_dat_o(ac97_dat_w), 363 411 .s8_adr_o(ac97_adr), 412 .s8_cti_o(ac97_cti), 364 413 .s8_sel_o(ac97_sel), 365 414 .s8_we_o(ac97_we), … … 371 420 .s9_dat_o(shader_dat_w), 372 421 .s9_adr_o(shader_adr), 422 .s9_cti_o(shader_cti), 373 423 .s9_sel_o(shader_sel), 374 424 .s9_we_o(shader_we), … … 380 430 .s10_dat_o(warp_dat_w), 381 431 .s10_adr_o(warp_adr), 432 .s10_cti_o(warp_cti), 382 433 .s10_sel_o(warp_sel), 383 434 .s10_we_o(warp_we), … … 398 449 // AEMB CPU 399 450 //--------------------------------------------------------------------------- 451 wire cpu_irq; 452 453 aeMB2_edk62 cpu( 454 .sys_clk_i(sys_clk), 455 .sys_rst_i(sys_rst), 456 .sys_int_i(cpu_irq), 457 .sys_ena_i(1'b1), 458 459 .iwb_wre_o(cpuibus_we), 460 .iwb_tag_o(), 461 .iwb_stb_o(cpuibus_stb), 462 .iwb_sel_o(cpuibus_sel), 463 .iwb_cyc_o(cpuibus_cyc), 464 .iwb_adr_o(cpuibus_adr[31:2]), 465 .iwb_dat_i(cpuibus_dat_r), 466 .iwb_ack_i(cpuibus_ack), 467 468 .dwb_wre_o(cpudbus_we), 469 .dwb_tag_o(), 470 .dwb_stb_o(cpudbus_stb), 471 .dwb_sel_o(cpudbus_sel), 472 .dwb_dat_o(cpudbus_dat_w), 473 .dwb_cyc_o(cpudbus_cyc), 474 .dwb_adr_o(cpudbus_adr[31:2]), 475 .dwb_dat_i(cpudbus_dat_r), 476 .dwb_ack_i(cpudbus_ack), 477 478 .xwb_adr_o(), 479 .xwb_wre_o(), 480 .xwb_tag_o(), 481 .xwb_stb_o(), 482 .xwb_sel_o(), 483 .xwb_dat_o(), 484 .xwb_cyc_o(), 485 .xwb_dat_i(32'hx), 486 .xwb_ack_i(1'b0) 487 ); 488 489 assign cpuibus_adr[1:0] = 2'b00; 490 assign cpudbus_adr[1:0] = 2'b00; 400 491 401 492 //--------------------------------------------------------------------------- … … 409 500 .mem3_file_name("../../software/bios/image3.ram") 410 501 ) bram ( 411 .clk_i( clk),412 .rst_i( rst),502 .clk_i(sys_clk), 503 .rst_i(sys_rst), 413 504 414 505 .wb_adr_i(bram_adr), … … 473 564 .baud(`BAUD_RATE) 474 565 ) uart ( 475 .clk( clk),476 .reset( rst),566 .clk(sys_clk), 567 .reset(sys_rst), 477 568 478 569 .wb_adr_i(uart_adr), … … 494 585 reg [19:0] rxcounter; 495 586 reg rxled; 496 always @(posedge clk) begin587 always @(posedge sys_clk) begin 497 588 if(~uart_rxd) 498 589 rxcounter <= 20'hfffff; … … 504 595 reg [19:0] txcounter; 505 596 reg txled; 506 always @(posedge clk) begin597 always @(posedge sys_clk) begin 507 598 if(~uart_txd) 508 599 txcounter <= 20'hfffff; … … 519 610 //--------------------------------------------------------------------------- 520 611 vga vga( 521 .sys_clk( clk),522 .sys_rst( rst),612 .sys_clk(sys_clk), 613 .sys_rst(sys_rst), 523 614 524 615 .wbc_adr_i(vga_adr), … … 547 638 `ifdef ENABLE_ACEUSB 548 639 aceusb aceusb( 549 .sys_clk( clk),550 .sys_rst( rst),640 .sys_clk(sys_clk), 641 .sys_rst(sys_rst), 551 642 552 643 .wb_cyc_i(aceusb_cyc), … … 582 673 `ifdef ENABLE_GPIO 583 674 gpio gpio ( 584 .clk( clk),585 .reset( rst),675 .clk(sys_clk), 676 .reset(sys_rst), 586 677 587 678 .wb_adr_i(gpio_adr),
