Changeset 183
- Timestamp:
- 11.11.2008 18:06:44 (2 months ago)
- Files:
-
- boards/xilinx-ml401/rtl/ddram.v (modified) (3 diffs)
- boards/xilinx-ml401/rtl/setup.v (modified) (1 diff)
- boards/xilinx-ml401/rtl/system.v (modified) (4 diffs)
- boards/xilinx-ml401/rtl/vga.v (modified) (1 diff)
- boards/xilinx-ml401/test/Makefile (added)
- boards/xilinx-ml401/test/system_tb.v (added)
- cores/brg64/rtl/brg64.v (modified) (1 diff)
- cores/conbus/rtl/conbus_highspeed.v (modified) (6 diffs)
- cores/uart/rtl/uart.v (modified) (1 diff)
- software/bios/crt0.S (modified) (3 diffs)
- software/bios/main.c (modified) (3 diffs)
- software/include.mak (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
boards/xilinx-ml401/rtl/ddram.v
r181 r183 64 64 65 65 `ifdef ENABLE_DDRAM 66 67 `ifndef SIMULATION 66 68 wire sys_clk2x; 67 69 wire sys_clkfb; … … 101 103 .RST(1'b0) 102 104 ); 103 105 `else 106 reg sys_clk2x; 107 initial sys_clk2x = 1'b0; 108 always @(posedge sys_clk) begin 109 #0.5 sys_clk2x = 1'b1; 110 #2.5 sys_clk2x = 1'b0; 111 #2.5 sys_clk2x = 1'b1; 112 #2.5 sys_clk2x = 1'b0; 113 end 114 `endif 115 116 `ifndef SIMULATION 104 117 DCM_BASE #( 105 118 .CLKDV_DIVIDE(1.5), // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 … … 136 149 .RST(1'b0) 137 150 ); 138 151 `else 152 assign sdram_clk_p = sys_clk; 153 assign sdram_clk_n = ~sys_clk; 154 `endif 139 155 140 156 hpdmc #( boards/xilinx-ml401/rtl/setup.v
r181 r183 26 26 * able to cut down synthesis times. 27 27 */ 28 `define ENABLE_GPIO29 `define ENABLE_ACEUSB30 `define ENABLE_DDRAM31 `define ENABLE_INTC32 `define ENABLE_TIMER28 //`define ENABLE_GPIO 29 //`define ENABLE_ACEUSB 30 //`define ENABLE_DDRAM 31 //`define ENABLE_INTC 32 //`define ENABLE_TIMER 33 33 //`define ENABLE_VGA 34 34 //`define ENABLE_AC97 boards/xilinx-ml401/rtl/system.v
r182 r183 85 85 wire sys_clk; 86 86 87 `ifndef SIMULATION 87 88 BUFG clkbuf( 88 89 .I(clkin), 89 90 .O(sys_clk) 90 91 ); 91 92 `else 93 assign sys_clk = clkin; 94 `endif 95 96 `ifndef SIMULATION 92 97 reg rst0; 93 98 reg rst1; … … 103 108 sys_rst <= rst_debounce != 16'h0000; 104 109 end 110 `else 111 wire sys_rst = resetin; 112 `endif 105 113 106 114 //------------------------------------------------------------------ … … 451 459 brgbus_dat_w; 452 460 453 wire [ 3:0] vgabus_sel,461 wire [7:0] vgabus_sel, 454 462 brgbus_sel; 455 463 … … 476 484 extmem_dat_w; 477 485 478 wire [ 3:0] extmem_sel;486 wire [7:0] extmem_sel; 479 487 480 488 wire extmem_we; boards/xilinx-ml401/rtl/vga.v
r180 r183 41 41 output [63:0] wb_dat_o, 42 42 input [63:0] wb_dat_i, 43 output [ 3:0] wb_sel_o,43 output [7:0] wb_sel_o, 44 44 output wb_cyc_o, 45 45 output wb_stb_o, cores/brg64/rtl/brg64.v
r180 r183 36 36 output [31:0] wb64_adr_o, 37 37 output [2:0] wb64_cti_o, 38 output [ 31:0] wb64_dat_o,39 input [ 31:0] wb64_dat_i,40 output [ 3:0] wb64_sel_o,38 output [63:0] wb64_dat_o, 39 input [63:0] wb64_dat_i, 40 output [7:0] wb64_sel_o, 41 41 output wb64_cyc_o, 42 42 output wb64_stb_o, cores/conbus/rtl/conbus_highspeed.v
r180 r183 36 36 input [31:0] m0_adr_i, 37 37 input [2:0] m0_cti_i, 38 input [ 3:0] m0_sel_i,38 input [7:0] m0_sel_i, 39 39 input m0_we_i, 40 40 input m0_cyc_i, … … 47 47 input [31:0] m1_adr_i, 48 48 input [2:0] m1_cti_i, 49 input [ 3:0] m1_sel_i,49 input [7:0] m1_sel_i, 50 50 input m1_we_i, 51 51 input m1_cyc_i, … … 58 58 input [31:0] m2_adr_i, 59 59 input [2:0] m2_cti_i, 60 input [ 3:0] m2_sel_i,60 input [7:0] m2_sel_i, 61 61 input m2_we_i, 62 62 input m2_cyc_i, … … 69 69 input [31:0] m3_adr_i, 70 70 input [2:0] m3_cti_i, 71 input [ 3:0] m3_sel_i,71 input [7:0] m3_sel_i, 72 72 input m3_we_i, 73 73 input m3_cyc_i, … … 80 80 output [31:0] s_adr_o, 81 81 output [2:0] s_cti_o, 82 output [ 3:0] s_sel_o,82 output [7:0] s_sel_o, 83 83 output s_we_o, 84 84 output s_cyc_o, … … 92 92 // address width + CTI + data width + byte select width 93 93 // + cyc + we + stb 94 `define mbusw_hs 32 + 3 + 64 + 4+ 394 `define mbusw_hs 32 + 3 + 64 + 8 + 3 95 95 96 96 wire [3:0] i_gnt_arb; cores/uart/rtl/uart.v
r180 r183 110 110 endcase 111 111 end else if (wb_wr & ~wb_ack_o ) begin 112 `ifdef SIMULATION 113 $display("UART TX: %x", tx_data); 114 `endif 112 115 wb_ack_o <= 1'b1; 113 116 software/bios/crt0.S
r178 r183 23 23 .ent _start 24 24 _start: brai _start1 25 _vector_sw_exception: brai _ exception_handler26 _vector_interrupt: brai _ interrupt_handler27 _vector_breakpoint: brai _ breakpoint_handler28 _vector_hw_exception: brai _ hw_exception_handler25 _vector_sw_exception: brai _start1 26 _vector_interrupt: brai _start1 27 _vector_breakpoint: brai _start1 28 _vector_hw_exception: brai _start1 29 29 30 30 /* ------ crt starts here --------- */ … … 33 33 la r13, r0, _SDA_BASE_ 34 34 la r2, r0, _SDA2_BASE_ 35 la r1, r0, _stack # stack is at end of block-ram 35 la r1, r0, _stack 36 37 brlid r15,_program_init /* lock one thread */ 38 nop 36 39 37 40 _crtinit: /* clear sbss */ … … 57 60 .Lendbss: 58 61 59 brlid r15,_program_init60 nop61 62 brlid r15,main # enter main program (ignoring parameters: r5, r6 & r7) 62 63 nop # fall throught to exit 63 64 .end _start 64 65 _interrupt_handler: brai 0xc0000008 # Jump to the get_interrupt label of the kernel, see arch/microblaze/head.S for more details66 _exception_handler:67 _breakpoint_handler:68 _hw_exception_handler:69 65 70 66 .globl exit # exit library call software/bios/main.c
r178 r183 153 153 static void memtest() 154 154 { 155 unsigned int testbuf[TESTBUF_SIZE];155 unsigned int *testbuf = (unsigned int *)0x80000000; 156 156 unsigned int i; 157 157 … … 251 251 int main(int argc, char **argv) 252 252 { 253 char buffer[1 28];253 char buffer[16]; 254 254 255 255 putsnonl(banner); … … 260 260 while(1) { 261 261 putsnonl("BIOS> "); 262 readstr(buffer, 1 28);262 readstr(buffer, 16); 263 263 do_command(buffer); 264 264 } software/include.mak
r178 r183 20 20 ASFLAGS=$(INCLUDES) -DTARGET=$(TARGET) 21 21 CFLAGS=-O2 -Wall -mtune=v5.00 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul $(INCLUDES) -DTARGET=$(TARGET) -fno-builtin 22 LDFLAGS=- s -nostdlib -nodefaultlibs22 LDFLAGS=-nostdlib -nodefaultlibs 23 23 24 24 # HW options
