Changeset 189

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Timestamp:
12.11.2008 16:26:38 (2 months ago)
Author:
seb
Message:

Pushing all Murphy-prone asynchronous logic into Xilinx primitives

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  • boards/xilinx-ml401/rtl/ddram.v

    r183 r189  
    6666 
    6767`ifndef SIMULATION 
    68 wire sys_clk2x; 
    69 wire sys_clkfb; 
    70  
    71 DCM_BASE #( 
    72         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 
    73  
    74         .CLKFX_DIVIDE(3),               // 1 to 32 
    75         .CLKFX_MULTIPLY(2),             // 2 to 32 
    76          
    77         .CLKIN_DIVIDE_BY_2("FALSE"), 
    78         .CLKIN_PERIOD(`CLOCK_PERIOD), 
    79         .CLKOUT_PHASE_SHIFT("NONE"), 
    80         .CLK_FEEDBACK("1X"), 
    81         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), 
    82         .DFS_FREQUENCY_MODE("LOW"), 
    83         .DLL_FREQUENCY_MODE("LOW"), 
    84         .DUTY_CYCLE_CORRECTION("TRUE"), 
    85         .FACTORY_JF(16'hC080), 
    86         .PHASE_SHIFT(0), 
    87         .STARTUP_WAIT("TRUE") 
    88 ) clkgen_2x ( 
    89         .CLK0(sys_clkfb), 
    90         .CLK90(), 
    91         .CLK180(), 
    92         .CLK270(), 
    93  
    94         .CLK2X(sys_clk2x), 
    95         .CLK2X180(), 
    96  
    97         .CLKDV(), 
    98         .CLKFX(), 
    99         .CLKFX180(), 
    100         .LOCKED(), 
    101         .CLKFB(sys_clkfb), 
    102         .CLKIN(sys_clk), 
    103         .RST(1'b0) 
    104 ); 
    105 `else 
    106 reg sys_clk2x; 
    107 initial sys_clk2x = 1'b0; 
    108 always @(posedge sys_clk) begin 
    109         #0.5 sys_clk2x = 1'b1; 
    110         #2.5 sys_clk2x = 1'b0; 
    111         #2.5 sys_clk2x = 1'b1; 
    112         #2.5 sys_clk2x = 1'b0; 
    113 end 
    114 `endif 
    115  
    116 `ifndef SIMULATION 
    11768DCM_BASE #( 
    11869        .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 
    …… 
    159110) hpdmc ( 
    160111        .sys_clk(sys_clk), 
    161         .sys_clk2x(sys_clk2x), 
    162112        .sys_rst(sys_rst), 
    163113 

  • cores/hpdmc/rtl/hpdmc_ddrio.v

    r185 r189  
    2222module hpdmc_ddrio( 
    2323        input clk, 
    24         input clk2x, 
    2524        input rst, 
    2625         
    …… 
    5049 
    5150reg wfifo_enable; 
    52 always @(posedge clk) wfifo_enable = op_write; 
     51always @(posedge rst, posedge clk) begin 
     52        if(rst) 
     53                wfifo_enable <= 1'b0; 
     54        else 
     55                wfifo_enable <= op_write; 
     56end 
    5357 
    54 reg [3:0] wfifomask1[0:3]; 
    55 reg [3:0] wfifomask0[0:3]; 
    56 reg [31:0] wfifo1[0:3]; 
    57 reg [31:0] wfifo0[0:3]; 
     58 
     59reg [7:0] wfifomask[0:3]; 
     60reg [63:0] wfifo[0:3]; 
    5861reg [1:0] wfifo_produce; 
    5962reg [1:0] wfifo_consume; 
    …… 
    6265always @(posedge clk) begin 
    6366        if(buffer_w_nextburst) begin 
    64                 wfifomask1[0] <= buffer_w_mask[7:4]; 
    65                 wfifomask1[1] <= 4'b1111; 
    66                 wfifomask1[2] <= 4'b1111; 
    67                 wfifomask1[3] <= 4'b1111; 
    68                 wfifomask0[0] <= buffer_w_mask[3:0]; 
    69                 wfifomask0[1] <= 4'b1111; 
    70                 wfifomask0[2] <= 4'b1111; 
    71                 wfifomask0[3] <= 4'b1111; 
    72                 wfifo1[0] <= buffer_w_dat[63:32]; 
    73                 wfifo0[0] <= buffer_w_dat[31:0]; 
     67                wfifomask[0] <= buffer_w_mask; 
     68                wfifomask[1] <= 8'hff; 
     69                wfifomask[2] <= 8'hff; 
     70                wfifomask[3] <= 8'hff; 
     71                wfifo[0] <= buffer_w_dat; 
    7472                wfifo_produce <= 2'b01; 
    7573        end else if(buffer_w_next) begin 
    7674                wfifo_produce <= wfifo_produce + 1; 
    77                 wfifomask1[wfifo_produce] <= buffer_w_mask[7:4]; 
    78                 wfifomask0[wfifo_produce] <= buffer_w_mask[3:0]; 
    79                 wfifo1[wfifo_produce] <= buffer_w_dat[63:32]; 
    80                 wfifo0[wfifo_produce] <= buffer_w_dat[31:0]; 
     75                wfifomask[wfifo_produce] <= buffer_w_mask; 
     76                wfifo[wfifo_produce] <= buffer_w_dat; 
    8177        end 
    8278end 
    8379 
    8480/* Reads from the Write FIFO */ 
    85 reg [3:0] wfifo_outmask; 
    86 reg [31:0] wfifo_out; 
    87 always @(posedge rst, negedge clk2x) begin 
     81always @(posedge clk) begin 
    8882        if(rst) begin 
    8983                wfifo_consume <= 2'b11; 
    90                 wfifo_outmask <= 4'b1111; 
    91                 wfifo_out <= 32'd0; 
    9284        end else begin 
    93                 if(clk) begin 
    94                         if(wfifo_enable) 
    95                                 wfifo_consume <= wfifo_consume + 2'd1; 
    96                         wfifo_outmask <= wfifomask0[wfifo_consume]; 
    97                         wfifo_out <= wfifo0[wfifo_consume]; 
    98                 end else begin 
    99                         wfifo_outmask <= wfifomask1[wfifo_consume]; 
    100                         wfifo_out <= wfifo1[wfifo_consume]; 
    101                 end 
     85                if(wfifo_enable) 
     86                        wfifo_consume <= wfifo_consume + 2'd1; 
    10287        end 
    10388end 
     89wire [7:0] wfifo_outmask = wfifomask[wfifo_consume]; 
     90wire [63:0] wfifo_out = wfifo[wfifo_consume]; 
    10491 
    10592/* Generate DQ/DQM/DQS */ 
    10693reg wfifo_enable_r; 
    107 always @(posedge clk) wfifo_enable_r <= wfifo_enable; 
    108 reg dq_drive; 
    109 always @(posedge rst, posedge clk2x) begin 
     94always @(posedge rst, posedge clk) begin 
    11095        if(rst) 
    111                 dq_drive <= 1'b0; 
    112         else begin 
    113                 if(~clk) begin 
    114                         if(~wfifo_enable_r) dq_drive <= 1'b0; 
    115                 end else begin 
    116                         if(wfifo_enable) dq_drive <= 1'b1; 
    117                 end 
    118         end 
     96                wfifo_enable_r <= 1'b0; 
     97        else 
     98                wfifo_enable_r <= wfifo_enable; 
    11999end 
    120100 
    121 assign sdram_dq = dq_drive ? wfifo_out : 32'hzzzzzzzz; 
    122 assign sdram_dqm = wfifo_outmask; 
     101/* 
     102 * We assume that the direct OR of two register outputs 
     103 * will be glitch-free. What's the fool-proof way of 
     104 * doing this ?! 
     105 */ 
     106wire [31:0] sdram_data_out; // DDR 
     107wire [63:0] sdram_data_in;  // SDR 
     108 
     109wire dq_drive = wfifo_enable | wfifo_enable_r; 
     110assign sdram_dq = dq_drive ? sdram_data_out : 32'hzzzzzzzz; 
    123111assign sdram_dqs = dq_drive ? {4{clk}} : 4'hz; 
    124112 
     113hpdmc_oddr4 #( 
     114        .DDR_CLK_EDGE("SAME_EDGE"), 
     115        .INIT(1'b0), 
     116        .SRTYPE("SYNC") 
     117) oddr_dqm ( 
     118        .Q(sdram_dqm), 
     119        .C(clk), 
     120        .CE(1'b1), 
     121        .D1(wfifo_outmask[7:4]), 
     122        .D2(wfifo_outmask[3:0]), 
     123        .R(rst), 
     124        .S(1'b0) 
     125); 
     126 
     127hpdmc_oddr32 #( 
     128        .DDR_CLK_EDGE("SAME_EDGE"), 
     129        .INIT(1'b0), 
     130        .SRTYPE("SYNC") 
     131) oddr_dq ( 
     132        .Q(sdram_data_out), 
     133        .C(clk), 
     134        .CE(1'b1), 
     135        .D1(wfifo_out[63:32]), 
     136        .D2(wfifo_out[31:0]), 
     137        .R(rst), 
     138        .S(1'b0) 
     139); 
     140 
     141hpdmc_iddr32 #( 
     142        .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), 
     143        .INIT_Q1(1'b0), 
     144        .INIT_Q2(1'b0), 
     145        .SRTYPE("SYNC") 
     146) iddr_dq ( 
     147        .Q1(sdram_data_in[63:32]), 
     148        .Q2(sdram_data_in[31:0]), 
     149        .C(C), 
     150        .CE(CE), 
     151        .D(sdram_dq), 
     152        .R(rst), 
     153        .S(1'b0) 
     154); 
    125155 
    126156/* 
    …… 
    128158 */ 
    129159 
    130 reg read_enable; 
    131160reg op_read_r; 
    132161always @(posedge clk) op_read_r <= op_read; 
    133 always @(negedge clk) read_enable <= op_read | op_read_r; 
     162wire read_enable; 
     163assign read_enable = op_read_r; 
    134164 
    135 reg [7:0] rfifo7[0:3]; 
    136 reg [7:0] rfifo6[0:3]; 
    137 reg [7:0] rfifo5[0:3]; 
    138 reg [7:0] rfifo4[0:3]; 
    139 reg [7:0] rfifo3[0:3]; 
    140 reg [7:0] rfifo2[0:3]; 
    141 reg [7:0] rfifo1[0:3]; 
    142 reg [7:0] rfifo0[0:3]; 
    143 reg [1:0] rfifo_produce0; 
    144 reg [1:0] rfifo_produce1; 
    145 reg [1:0] rfifo_produce2; 
    146 reg [1:0] rfifo_produce3; 
     165reg [63:0] rfifo[0:3]; 
     166reg [1:0] rfifo_produce; 
    147167reg [1:0] rfifo_consume; 
    148168 
    149169/* Writes to the Read FIFO */ 
    150  
    151 /* DQS0 */ 
    152 always @(posedge sdram_dqs[0]) begin 
    153         if(read_enable) 
    154                 rfifo4[rfifo_produce0] <= sdram_dq[7:0]; 
    155 end 
    156 always @(posedge rst, negedge sdram_dqs[0]) begin 
     170always @(posedge rst, posedge clk) begin 
    157171        if(rst) 
    158                 rfifo_produce0 <= 2'b00; 
     172                rfifo_produce <= 2'd0; 
    159173        else begin 
    160174                if(read_enable) begin 
    161                         rfifo_produce0 <= rfifo_produce0 + 1; 
    162                         rfifo0[rfifo_produce0] <= sdram_dq[7:0]; 
    163                 end 
    164         end 
    165 end 
    166  
    167 /* DQS1 */ 
    168 always @(posedge sdram_dqs[1]) begin 
    169         if(read_enable) 
    170                 rfifo5[rfifo_produce1] <= sdram_dq[15:8]; 
    171 end 
    172 always @(posedge rst or negedge sdram_dqs[1]) begin 
    173         if(rst) 
    174                 rfifo_produce1 <= 2'b00; 
    175         else begin 
    176                 if(read_enable) begin 
    177                         rfifo_produce1 <= rfifo_produce1 + 1; 
    178                         rfifo1[rfifo_produce1] <= sdram_dq[15:8]; 
    179                 end 
    180         end 
    181 end 
    182  
    183 /* DQS2 */ 
    184 always @(posedge sdram_dqs[2]) begin 
    185         if(read_enable) 
    186                 rfifo6[rfifo_produce2] <= sdram_dq[23:16]; 
    187 end 
    188 always @(posedge rst or negedge sdram_dqs[2]) begin 
    189         if(rst) 
    190                 rfifo_produce2 <= 2'b00; 
    191         else begin 
    192                 if(read_enable) begin 
    193                         rfifo_produce2 <= rfifo_produce2 + 1; 
    194                         rfifo2[rfifo_produce2] <= sdram_dq[23:16]; 
    195                 end 
    196         end 
    197 end 
    198  
    199 /* DQS3 */ 
    200 always @(posedge sdram_dqs[3]) begin 
    201         if(read_enable) 
    202                 rfifo7[rfifo_produce3] <= sdram_dq[31:24]; 
    203 end 
    204 always @(posedge rst, negedge sdram_dqs[3]) begin 
    205         if(rst) 
    206                 rfifo_produce3 <= 2'b00; 
    207         else begin 
    208                 if(read_enable) begin 
    209                         rfifo_produce3 <= rfifo_produce3 + 1; 
    210                         rfifo3[rfifo_produce3] <= sdram_dq[31:24]; 
     175                        rfifo_produce <= rfifo_produce + 2'd1; 
     176                        rfifo[rfifo_produce] <= sdram_data_in; 
    211177                end 
    212178        end 
    …… 
    216182always @(posedge rst, posedge clk) begin 
    217183        if(rst) 
    218                 rfifo_consume <= 2'b00; 
     184                rfifo_consume <= 2'd0; 
    219185        else begin 
    220186                if(buffer_r_nextburst) 
    221                         rfifo_consume <= 2'b00; 
     187                        rfifo_consume <= 2'd0; 
    222188                else if(buffer_r_next) 
    223                         rfifo_consume <= rfifo_consume + 1; 
     189                        rfifo_consume <= rfifo_consume + 2'd1; 
    224190        end 
    225191end 
    226192 
    227 assign buffer_r_dat = {rfifo7[rfifo_consume], 
    228                         rfifo6[rfifo_consume], 
    229                         rfifo5[rfifo_consume], 
    230                         rfifo4[rfifo_consume], 
    231                         rfifo3[rfifo_consume], 
    232                         rfifo2[rfifo_consume], 
    233                         rfifo1[rfifo_consume], 
    234                         rfifo0[rfifo_consume]}; 
     193assign buffer_r_dat = rfifo[rfifo_consume]; 
    235194 
    236195endmodule 

  • cores/hpdmc/test/Makefile

    r150 r189  
    1 SOURCES_DDRIO=tb_ddrio.v ../rtl/hpdmc_ddrio.v 
     1SOURCES_DDRIO=tb_ddrio.v oddr.v iddr.v ../rtl/hpdmc_oddr32.v ../rtl/hpdmc_oddr4.v ../rtl/hpdmc_iddr32.v ../rtl/hpdmc_ddrio.v 
    22SOURCES_MODEL=tb_model.v ddr.v 
    3 SOURCES_HPDMC=tb_hpdmc.v ddr.v ../rtl/hpdmc_conf.v ../rtl/hpdmc_ddrio.v ../rtl/hpdmc_scheduler.v ../rtl/hpdmc.v 
     3SOURCES_HPDMC=tb_hpdmc.v ddr.v oddr.v iddr.v ../rtl/hpdmc_conf.v ../rtl/hpdmc_oddr32.v ../rtl/hpdmc_oddr4.v ../rtl/hpdmc_iddr32.v ../rtl/hpdmc_ddrio.v ../rtl/hpdmc_scheduler.v ../rtl/hpdmc.v 
    44 
    55all: hpdmc 

  • cores/hpdmc/test/tb_ddrio.v

    r150 r189  
    2929module tb_ddrio(); 
    3030 
    31 /* clk should have a small delay relative to clk2x 
    32  * to meet the setup/hold time requirement of registers 
    33  * synchronous to clk2x whose input depend on clk. 
    34  */ 
    35 reg clk_p; 
    36 initial clk_p = 1'b0; 
    37 always #5 clk_p = ~clk; 
    3831reg clk; 
    3932initial clk = 1'b0; 
    40 always @(clk_p) #0.5 clk <= clk_p; 
    41  
    42 reg clk2x; 
    43 initial clk2x = 1'b1; 
    44 always #2.5 clk2x = ~clk2x; 
     33always #5 clk = ~clk; 
    4534 
    4635reg rst; 
    …… 
    6352hpdmc_ddrio ddrio( 
    6453        .clk(clk), 
    65         .clk2x(clk2x), 
    6654        .rst(rst), 
    6755         

  • cores/hpdmc/test/verilog.log

    r150 r189  
    33  All Rights reserved.  Licensed under the GNU General Public License (GPL). 
    44  See the 'COPYING' file for details.  NO WARRANTY provided. 
    5 Today is Wed Oct 29 11:22:15 2008. 
    6 Compiling source file "tb_hpdmc.v" 
    7 Compiling source file "ddr.v" 
    8 Compiling source file "../rtl/hpdmc_conf.v" 
     5Today is Wed Nov 12 16:16:24 2008. 
     6Compiling source file "tb_ddrio.v" 
     7Compiling source file "oddr.v" 
     8Compiling source file "iddr.v" 
     9Compiling source file "../rtl/hpdmc_oddr32.v" 
     10Compiling source file "../rtl/hpdmc_oddr4.v" 
     11Compiling source file "../rtl/hpdmc_iddr32.v" 
    912Compiling source file "../rtl/hpdmc_ddrio.v" 
    10 Compiling source file "../rtl/hpdmc_scheduler.v" 
    11 Compiling source file "../rtl/hpdmc.v" 
    12 **ddr.v(159) WARN** [620] array mem_array has 16777216 cells - standard only requires maximum of 16777215 
    1313Highest level modules: 
    14 tb_hpdmc 
     14tb_ddrio 
    1515 
    16 Configuration Write: 00000000=00000007 acked in           1 clocks 
    17 Configuration Write: 00000004=0000400b acked in           1 clocks 
    18 tb_hpdmc.sdram1.Control_Logic: At time 200066.000 ns PRE  : Addr[10] = 1, Bank = 00 
    19 tb_hpdmc.sdram0.Control_Logic: At time 200066.000 ns PRE  : Addr[10] = 1, Bank = 00 
    20 Configuration Write: 00000004=0002000f acked in           1 clocks 
    21 tb_hpdmc.sdram1.Control_Logic: At time 200106.000 ns EMR  : Extended Mode Register 
    22 tb_hpdmc.sdram1.Control_Logic: At time 200106.000 ns EMR  : Enable DLL 
    23 tb_hpdmc.sdram0.Control_Logic: At time 200106.000 ns EMR  : Extended Mode Register 
    24 tb_hpdmc.sdram0.Control_Logic: At time 200106.000 ns EMR  : Enable DLL 
    25 Configuration Write: 00000004=0000123f acked in           1 clocks 
    26 tb_hpdmc.sdram1.Control_Logic: At time 200146.000 ns LMR  : Load Mode Register 
    27 tb_hpdmc.sdram1.Control_Logic: At time 200146.000 ns LMR  : Burst Length = 8 
    28 tb_hpdmc.sdram1.Control_Logic: At time 200146.000 ns LMR  : CAS Latency = 2 
    29 tb_hpdmc.sdram0.Control_Logic: At time 200146.000 ns LMR  : Load Mode Register 
    30 tb_hpdmc.sdram0.Control_Logic: At time 200146.000 ns LMR  : Burst Length = 8 
    31 tb_hpdmc.sdram0.Control_Logic: At time 200146.000 ns LMR  : CAS Latency = 2 
    32 Configuration Write: 00000004=0000400b acked in           1 clocks 
    33 tb_hpdmc.sdram1.Control_Logic: At time 202166.000 ns PRE  : Addr[10] = 1, Bank = 00 
    34 tb_hpdmc.sdram0.Control_Logic: At time 202166.000 ns PRE  : Addr[10] = 1, Bank = 00 
    35 Configuration Write: 00000004=0000000d acked in           1 clocks 
    36 tb_hpdmc.sdram1.Control_Logic: At time 202206.000 ns AREF : Auto Refresh 
    37 tb_hpdmc.sdram1: at time 202206.000 ns MEMORY:  Power Up and Initialization Sequence is complete 
    38 tb_hpdmc.sdram0.Control_Logic: At time 202206.000 ns AREF : Auto Refresh 
    39 tb_hpdmc.sdram0: at time 202206.000 ns MEMORY:  Power Up and Initialization Sequence is complete 
    40 Configuration Write: 00000004=0000000d acked in           1 clocks 
    41 tb_hpdmc.sdram1.Control_Logic: At time 202306.000 ns AREF : Auto Refresh 
    42 tb_hpdmc.sdram0.Control_Logic: At time 202306.000 ns AREF : Auto Refresh 
    43 Configuration Write: 00000004=0000023f acked in           1 clocks 
    44 tb_hpdmc.sdram1.Control_Logic: At time 202406.000 ns LMR  : Load Mode Register 
    45 tb_hpdmc.sdram1.Control_Logic: At time 202406.000 ns LMR  : Burst Length = 8 
    46 tb_hpdmc.sdram1.Control_Logic: At time 202406.000 ns LMR  : CAS Latency = 2 
    47 tb_hpdmc.sdram0.Control_Logic: At time 202406.000 ns LMR  : Load Mode Register 
    48 tb_hpdmc.sdram0.Control_Logic: At time 202406.000 ns LMR  : Burst Length = 8 
    49 tb_hpdmc.sdram0.Control_Logic: At time 202406.000 ns LMR  : CAS Latency = 2 
    50 Configuration Write: 00000000=00000004 acked in           1 clocks 
    51 tb_hpdmc.sdram1.Control_Logic: At time 204436.000 ns PRE  : Addr[10] = 1, Bank = xx 
    52 tb_hpdmc.sdram0.Control_Logic: At time 204436.000 ns PRE  : Addr[10] = 1, Bank = xx 
    53 tb_hpdmc.sdram1.Control_Logic: At time 204466.000 ns AREF : Auto Refresh 
    54 tb_hpdmc.sdram0.Control_Logic: At time 204466.000 ns AREF : Auto Refresh 
    55 wstate:  0-> 3 
    56 wstate:  3-> 3 
    57 wstate:  3-> 3 
    58 wstate:  3-> 3 
    59 tb_hpdmc.sdram1.Control_Logic: At time 204756.000 ns ACT  : Bank = 0, Row = 0000 
    60 tb_hpdmc.sdram0.Control_Logic: At time 204756.000 ns ACT  : Bank = 0, Row = 0000 
    61 wstate:  3-> 3 
    62 wstate:  3-> 3 
    63 Memory Write : 00000000=12153524c0895e81 acked in           6 clocks 
    64 wstate:  3-> 4 
    65 At time 204786.000 ns WRITE: Bank = 0, Col = 000 
    66 At time 204786.000 ns WRITE: Bank = 0, Col = 000 
    67 (burst continuing)     8484d609b1f05663 
    68 wstate:  4-> 4 
    69 (burst continuing)     06b97b0d46df998d 
    70 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204801.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 1215 
    71 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204801.000 ns WRITE: Bank = 0, Row = 0000, Col = 000, Data = 3524 
    72 wstate:  4-> 4 
    73 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204806.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = c089 
    74 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204806.000 ns WRITE: Bank = 0, Row = 0000, Col = 001, Data = 5e81 
    75 (burst continuing)     b2c2846589375212 
    76 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204811.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = 8484 
    77 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204811.000 ns WRITE: Bank = 0, Row = 0000, Col = 002, Data = d609 
    78 wstate:  4-> 0 
    79 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204816.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = b1f0 
    80 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204816.000 ns WRITE: Bank = 0, Row = 0000, Col = 003, Data = 5663 
    81 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204821.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 06b9 
    82 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204821.000 ns WRITE: Bank = 0, Row = 0000, Col = 004, Data = 7b0d 
    83 wstate:  0-> 3 
    84 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204826.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 46df 
    85 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204826.000 ns WRITE: Bank = 0, Row = 0000, Col = 005, Data = 998d 
    86 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204831.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = b2c2 
    87 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204831.000 ns WRITE: Bank = 0, Row = 0000, Col = 006, Data = 8465 
    88 wstate:  3-> 3 
    89 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204836.000 ns WRITE: Bank = 0, Row = 0000, Col = 007, Data = 8937 
    90 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204836.000 ns WRITE: Bank = 0, Row = 0000, Col = 007, Data = 5212 
    91 wstate:  3-> 3 
    92 Memory Write : 00000020=00f3e30106d7cd0d acked in           3 clocks 
    93 wstate:  3-> 4 
    94 At time 204856.000 ns WRITE: Bank = 0, Col = 008 
    95 At time 204856.000 ns WRITE: Bank = 0, Col = 008 
    96 (burst continuing)     3b23f1761e8dcd3d 
    97 wstate:  4-> 4 
    98 (burst continuing)     76d457ed462df78c 
    99 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204871.000 ns WRITE: Bank = 0, Row = 0000, Col = 008, Data = 00f3 
    100 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204871.000 ns WRITE: Bank = 0, Row = 0000, Col = 008, Data = e301 
    101 wstate:  4-> 4 
    102 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204876.000 ns WRITE: Bank = 0, Row = 0000, Col = 009, Data = 06d7 
    103 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204876.000 ns WRITE: Bank = 0, Row = 0000, Col = 009, Data = cd0d 
    104 (burst continuing)     7cfde9f9e33724c6 
    105 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204881.000 ns WRITE: Bank = 0, Row = 0000, Col = 00a, Data = 3b23 
    106 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204881.000 ns WRITE: Bank = 0, Row = 0000, Col = 00a, Data = f176 
    107 wstate:  4-> 0 
    108 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204886.000 ns WRITE: Bank = 0, Row = 0000, Col = 00b, Data = 1e8d 
    109 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204886.000 ns WRITE: Bank = 0, Row = 0000, Col = 00b, Data = cd3d 
    110 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204891.000 ns WRITE: Bank = 0, Row = 0000, Col = 00c, Data = 76d4 
    111 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204891.000 ns WRITE: Bank = 0, Row = 0000, Col = 00c, Data = 57ed 
    112 wstate:  0-> 3 
    113 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204896.000 ns WRITE: Bank = 0, Row = 0000, Col = 00d, Data = 462d 
    114 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204896.000 ns WRITE: Bank = 0, Row = 0000, Col = 00d, Data = f78c 
    115 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204901.000 ns WRITE: Bank = 0, Row = 0000, Col = 00e, Data = 7cfd 
    116 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204901.000 ns WRITE: Bank = 0, Row = 0000, Col = 00e, Data = e9f9 
    117 wstate:  3-> 3 
    118 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204906.000 ns WRITE: Bank = 0, Row = 0000, Col = 00f, Data = e337 
    119 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204906.000 ns WRITE: Bank = 0, Row = 0000, Col = 00f, Data = 24c6 
    120 wstate:  3-> 3 
    121 Memory Write : 00000040=e2f784c5d513d2aa acked in           3 clocks 
    122 wstate:  3-> 4 
    123 At time 204926.000 ns WRITE: Bank = 0, Col = 010 
    124 At time 204926.000 ns WRITE: Bank = 0, Col = 010 
    125 (burst continuing)     72aff7e5bbd27277 
    126 wstate:  4-> 4 
    127 (burst continuing)     8932d61247ecdb8f 
    128 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204941.000 ns WRITE: Bank = 0, Row = 0000, Col = 010, Data = e2f7 
    129 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204941.000 ns WRITE: Bank = 0, Row = 0000, Col = 010, Data = 84c5 
    130 wstate:  4-> 4 
    131 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204946.000 ns WRITE: Bank = 0, Row = 0000, Col = 011, Data = d513 
    132 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204946.000 ns WRITE: Bank = 0, Row = 0000, Col = 011, Data = d2aa 
    133 (burst continuing)     793069f2e77696ce 
    134 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204951.000 ns WRITE: Bank = 0, Row = 0000, Col = 012, Data = 72af 
    135 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204951.000 ns WRITE: Bank = 0, Row = 0000, Col = 012, Data = f7e5 
    136 wstate:  4-> 0 
    137 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204956.000 ns WRITE: Bank = 0, Row = 0000, Col = 013, Data = bbd2 
    138 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204956.000 ns WRITE: Bank = 0, Row = 0000, Col = 013, Data = 7277 
    139 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204961.000 ns WRITE: Bank = 0, Row = 0000, Col = 014, Data = 8932 
    140 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204961.000 ns WRITE: Bank = 0, Row = 0000, Col = 014, Data = d612 
    141 wstate:  0-> 3 
    142 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204966.000 ns WRITE: Bank = 0, Row = 0000, Col = 015, Data = 47ec 
    143 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204966.000 ns WRITE: Bank = 0, Row = 0000, Col = 015, Data = db8f 
    144 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204971.000 ns WRITE: Bank = 0, Row = 0000, Col = 016, Data = 7930 
    145 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204971.000 ns WRITE: Bank = 0, Row = 0000, Col = 016, Data = 69f2 
    146 wstate:  3-> 3 
    147 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 204976.000 ns WRITE: Bank = 0, Row = 0000, Col = 017, Data = e776 
    148 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 204976.000 ns WRITE: Bank = 0, Row = 0000, Col = 017, Data = 96ce 
    149 wstate:  3-> 3 
    150 wstate:  3-> 3 
    151 tb_hpdmc.sdram1.Control_Logic: At time 204996.000 ns PRE  : Addr[10] = 0, Bank = 00 
    152 tb_hpdmc.sdram0.Control_Logic: At time 204996.000 ns PRE  : Addr[10] = 0, Bank = 00 
    153 wstate:  3-> 3 
    154 wstate:  3-> 3 
    155 wstate:  3-> 3 
    156 tb_hpdmc.sdram1.Control_Logic: At time 205026.000 ns ACT  : Bank = 0, Row = 0012 
    157 tb_hpdmc.sdram0.Control_Logic: At time 205026.000 ns ACT  : Bank = 0, Row = 0012 
    158 wstate:  3-> 3 
    159 wstate:  3-> 3 
    160 Memory Write : 00012340=f4007ae8e2ca4ec5 acked in           9 clocks 
    161 wstate:  3-> 4 
    162 At time 205056.000 ns WRITE: Bank = 0, Col = 0d0 
    163 At time 205056.000 ns WRITE: Bank = 0, Col = 0d0 
    164 (burst continuing)     2e58495cde8e28bd 
    165 wstate:  4-> 4 
    166 (burst continuing)     96ab582db2a72665 
    167 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205071.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d0, Data = f400 
    168 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205071.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d0, Data = 7ae8 
    169 wstate:  4-> 4 
    170 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205076.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d1, Data = e2ca 
    171 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205076.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d1, Data = 4ec5 
    172 (burst continuing)     b1ef62630573870a 
    173 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205081.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d2, Data = 2e58 
    174 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205081.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d2, Data = 495c 
    175 wstate:  4-> 0 
    176 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205086.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d3, Data = de8e 
    177 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205086.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d3, Data = 28bd 
    178 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205091.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d4, Data = 96ab 
    179 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205091.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d4, Data = 582d 
    180 wstate:  0-> 3 
    181 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205096.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d5, Data = b2a7 
    182 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205096.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d5, Data = 2665 
    183 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205101.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d6, Data = b1ef 
    184 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205101.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d6, Data = 6263 
    185 wstate:  3-> 3 
    186 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205106.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d7, Data = 0573 
    187 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205106.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d7, Data = 870a 
    188 wstate:  3-> 3 
    189 Memory Write : 00012360=c03b228010642120 acked in           3 clocks 
    190 wstate:  3-> 4 
    191 At time 205126.000 ns WRITE: Bank = 0, Col = 0d8 
    192 At time 205126.000 ns WRITE: Bank = 0, Col = 0d8 
    193 (burst continuing)     557845aacecccc9d 
    194 wstate:  4-> 4 
    195 (burst continuing)     cb203e968983b813 
    196 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205141.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d8, Data = c03b 
    197 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205141.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d8, Data = 2280 
    198 wstate:  4-> 4 
    199 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205146.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d9, Data = 1064 
    200 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205146.000 ns WRITE: Bank = 0, Row = 0012, Col = 0d9, Data = 2120 
    201 (burst continuing)     86bc380da9a7d653 
    202 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205151.000 ns WRITE: Bank = 0, Row = 0012, Col = 0da, Data = 5578 
    203 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205151.000 ns WRITE: Bank = 0, Row = 0012, Col = 0da, Data = 45aa 
    204 wstate:  4-> 0 
    205 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205156.000 ns WRITE: Bank = 0, Row = 0012, Col = 0db, Data = cecc 
    206 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205156.000 ns WRITE: Bank = 0, Row = 0012, Col = 0db, Data = cc9d 
    207 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205161.000 ns WRITE: Bank = 0, Row = 0012, Col = 0dc, Data = cb20 
    208 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205161.000 ns WRITE: Bank = 0, Row = 0012, Col = 0dc, Data = 3e96 
    209 wstate:  0-> 1 
    210 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205166.000 ns WRITE: Bank = 0, Row = 0012, Col = 0dd, Data = 8983 
    211 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205166.000 ns WRITE: Bank = 0, Row = 0012, Col = 0dd, Data = b813 
    212 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205171.000 ns WRITE: Bank = 0, Row = 0012, Col = 0de, Data = 86bc 
    213 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205171.000 ns WRITE: Bank = 0, Row = 0012, Col = 0de, Data = 380d 
    214 wstate:  1-> 1 
    215 tb_hpdmc.sdram1.Write_FIFO_DM_Mask_Logic: At time 205176.000 ns WRITE: Bank = 0, Row = 0012, Col = 0df, Data = a9a7 
    216 tb_hpdmc.sdram0.Write_FIFO_DM_Mask_Logic: At time 205176.000 ns WRITE: Bank = 0, Row = 0012, Col = 0df, Data = d653 
    217 wstate:  1-> 1 
    218 wstate:  1-> 1 
    219 tb_hpdmc.sdram1.Control_Logic: At time 205196.000 ns PRE  : Addr[10] = 0, Bank = 00 
    220 tb_hpdmc.sdram0.Control_Logic: At time 205196.000 ns PRE  : Addr[10] = 0, Bank = 00 
    221 wstate:  1-> 1 
    222 wstate:  1-> 1 
    223 wstate:  1-> 1 
    224 tb_hpdmc.sdram1.Control_Logic: At time 205226.000 ns ACT  : Bank = 0, Row = 0000 
    225 tb_hpdmc.sdram0.Control_Logic: At time 205226.000 ns ACT  : Bank = 0, Row = 0000 
    226 wstate:  1-> 1 
    227 wstate:  1-> 1 
    228 wstate:  1-> 1 
    229 tb_hpdmc.sdram1.Control_Logic: At time 205256.000 ns READ : Bank = 0, Col = 000 
    230 tb_hpdmc.sdram0.Control_Logic: At time 205256.000 ns READ : Bank = 0, Col = 000 
    231 wstate:  1-> 1 
    232 wstate:  1-> 1 
    233 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205276.000 ns READ : Bank = 0, Row = 0000, Col = 000, Data = 1215 
    234 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205276.000 ns READ : Bank = 0, Row = 0000, Col = 000, Data = 3524 
    235 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205281.000 ns READ : Bank = 0, Row = 0000, Col = 001, Data = c089 
    236 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205281.000 ns READ : Bank = 0, Row = 0000, Col = 001, Data = 5e81 
    237 wstate:  1-> 1 
    238 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205286.000 ns READ : Bank = 0, Row = 0000, Col = 002, Data = 8484 
    239 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205286.000 ns READ : Bank = 0, Row = 0000, Col = 002, Data = d609 
    240 Memory Read : 00000000=12153524c0895e81 acked in          13 clocks 
    241 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205291.000 ns READ : Bank = 0, Row = 0000, Col = 003, Data = b1f0 
    242 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205291.000 ns READ : Bank = 0, Row = 0000, Col = 003, Data = 5663 
    243 wstate:  1-> 2 
    244 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205296.000 ns READ : Bank = 0, Row = 0000, Col = 004, Data = 06b9 
    245 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205296.000 ns READ : Bank = 0, Row = 0000, Col = 004, Data = 7b0d 
    246 (burst continuing)     8484d609b1f05663 
    247 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205301.000 ns READ : Bank = 0, Row = 0000, Col = 005, Data = 46df 
    248 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205301.000 ns READ : Bank = 0, Row = 0000, Col = 005, Data = 998d 
    249 wstate:  2-> 2 
    250 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205306.000 ns READ : Bank = 0, Row = 0000, Col = 006, Data = b2c2 
    251 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205306.000 ns READ : Bank = 0, Row = 0000, Col = 006, Data = 8465 
    252 (burst continuing)     06b97b0d46df998d 
    253 tb_hpdmc.sdram1.Dq_Dqs_Drivers: At time 205311.000 ns READ : Bank = 0, Row = 0000, Col = 007, Data = 8937 
    254 tb_hpdmc.sdram0.Dq_Dqs_Drivers: At time 205311.000 ns READ : Bank = 0, Row = 0000, Col = 007, Data = 5212 
    255 wstate:  2-> 2 
    256 (burst continuing)     b2c2846589375212 
    257 wstate:  2-> 0 
    258 Halted at location **tb_hpdmc.v(465) time 205326500 ps from call to $finish. 
    259   There were 0 error(s), 1 warning(s), and 146 inform(s). 
     16Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance tb_ddrio.ddrio.oddr_dqm.oddr0 is set to E_ED\000\000\000SAME_EDGE.  Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE. 
     17Halted at location **oddr.v(48) time 0 ps from call to $finish. 
     18  There were 0 error(s), 0 warning(s), and 40 inform(s).