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Changeset 202

Timestamp:

20.11.2008 17:43:38 (2 months ago)

Author:

seb

Message:

Different clock inputs for DQS, IDDR and ODDR

Files:

r199	r202
39	39	parameter sdram_columndepth = 8
40	40	) (
41		~~/* Clock and Reset signals are shared between all interfaces */~~
42	41	input sys_clk,
	42	/* Fine clock tuning in case Murphy shows up. These clocks can be sys_clk or
	43	* have some phase difference, depending on your setup. */
	44	input read_clk,
	45	input write_clk,
	46	input dqs_clk,
	47
43	48	input sys_rst,
44	49
…	…
288	293
289	294	hpdmc_datactl datactl(
290		.sys_clk(sys_clk),
291		.sdram_rst(sdram_rst),
	295	.read_clk(read_clk),
	296	.write_clk(write_clk),
	297	.dqs_clk(dqs_clk),
292	298
293	299	.read(read),

r199	r202
21	21
22	22	module hpdmc_ddrio(
23		input sys_clk,
24		input sdram_rst,
	23	input read_clk,
	24	input write_clk,
	25	input dqs_clk,
25	26
26	27	input direction,
…	…
35	36
36	37	assign sdram_dq = direction ? sdram_data_out : 32'hzzzzzzzz;
37
38		`ifdef SIMULATION
39		reg clk_dqs;
40		always @(clk) #1 clk_dqs <= clk;
41		`else
42		wire clk_dqs = sys_clk;
43		`endif
44
45		assign sdram_dqs = direction ? {4{clk_dqs}} : 4'hz;
	38	assign sdram_dqs = direction ? {4{dqs_clk}} : 4'hz;
46	39
47	40	hpdmc_oddr4 oddr_dqm(
48	41	.Q(sdram_dqm),
49		.C(clk),
	42	.C(write_clk),
50	43	.CE(1'b1),
51	44	.D1(mo[7:4]),
…	…
57	50	hpdmc_oddr32 oddr_dq(
58	51	.Q(do),
59		.C(clk),
	52	.C(write_clk),
60	53	.CE(1'b1),
61	54	.D1(buffer_w_dat[63:32]),
…	…
68	61	.Q1(di[31:0]),
69	62	.Q2(di[63:32]),
70		.C(clk),
	63	.C(read_clk),
71	64	.CE(1'b1),
72	65	.D(sdram_dq),