Timeline

20.11.2008:

19:54 Changeset [205] by seb: Fixed bugs
18:17 Changeset [204] by seb: Fixed syntax and typos
17:50 Changeset [203] by seb: Testbench update
17:43 Changeset [202] by seb: Different clock inputs for DQS, IDDR and ODDR
12:34 Changeset [201] by seb: Single bus scheduler

21:03 Changeset [191] by seb: Doc update
19:05 Changeset [190] by seb: Doc about the new memory controller architecture

16:26 Changeset [189] by seb: Pushing all Murphy-prone asynchronous logic into Xilinx primitives
14:33 Changeset [188] by seb: Multi bit DDR registers
12:28 Changeset [187] by seb: Simulations models for ODDR and IDDR

23:16 Changeset [179] by seb: Linker scripts and memory map update
22:48 Changeset [178] by seb: Software update
20:48 Changeset [177] by seb: High speed conbus
20:23 Changeset [176] by seb: New conbus
15:46 Changeset [175] by seb: Put all files at the top level, while working around SVN bugs
15:45 Changeset [174] by seb: Put all files at the top level, while working around SVN bugs
15:45 Changeset [173] by seb: Put all files at the top level, while working around SVN bugs
15:45 Changeset [172] by seb: Put all files at the top level, while working around SVN bugs
15:45 Changeset [171] by seb: Put all files at the top level, while working around SVN bugs
15:45 Changeset [170] by seb: Put all files at the top level, while working around SVN bugs
15:45 Changeset [169] by seb: Put all files at the top level, while working around SVN bugs
15:43 Changeset [168] by seb: Put all files at the top level, while working around SVN bugs
15:43 Changeset [167] by seb: Put all files at the top level, while working around SVN bugs
15:43 Changeset [166] by seb: Put all files at the top level, while working around SVN bugs
15:42 Changeset [165] by seb: Put all files at the top level, while working around SVN bugs
15:40 Changeset [164] by seb: Board files reorganization
15:30 Changeset [163] by seb: New makefiles for doc + small core improvements
11:42 Changeset [162] by seb: Interrupt controller

16:44 Changeset [155] by seb: Added AEMB
16:35 Changeset [154] by seb: Added AC97 from OC
16:26 Changeset [153] by seb: Doc update
14:25 Changeset [152] by seb: Fixed paths in testbenches + UART, timer and GPIO cleanup
13:47 Changeset [151] by seb: Moved testbenches
12:36 Changeset [150] by seb: Added HPDMC
12:35 Changeset [149] by seb: Removed AC97 (will sync with OC)
12:34 Changeset [148] by seb: Starting file reorganization
12:30 Changeset [147] by seb: Removed files for cores to be replaced

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